10. CACHE Instructions

10.10 Index Store Tag (S)

Index Store Tag (S) stores fields from the CP0 TagLo and TagHi registers into the secondary cache tag and MRU array fields. The PA[Cachesize-2..Blocksize] defines the address and PA[0] defines the way to be read.

The following mapping defines the operation:

Tag ECC bits = TagLo[6:0]

Virtual index bits = TagLo[8:7]

State bits = TagLo[11:10]

Tag[35:18] = TagLo[31:14]

Tag[39:36] = TagHi[3:0]

MRU bit = TagHi[31]

All Tag fields, including ECC, are directly written.

Parity check is suppressed for all Index Store Tags.

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